This invention relates to methods of integrated circuit fabrication and the devices produced thereby.
It is becoming increasingly popular in the manufacture of modern integrated circuits to include intergral capacitors within the integrated circuit. For example, many DRAM designs and many analog designs include intergral capacitors within an integrated circuit chip. Often the capacitors are made by trenching into the silicon substrate.
Those concerned with the development of integrated circuits have consistently sought new capacitor designs and methods for forming these designs. Of particular interest are fabrication methods which produce capacitors with increased capacitance within small volumes.
An improved method of integrated circuit fabrication and an improved integrated circuit address the above concerns.
A first illustrative embodiment includes a method of integrated circuit fabrication which includes forming a conductive plug having an outer surface with grooves;
forming a dielectric which fills the grooves; and
forming a conductive material over the dielectric; the conductive plug, the dielectric, and the conductive material together comprising a capacitor.
A second illustrative embodiment includes a method of integrated circuit fabrication which includes forming a patterned photoresist upon a first material layer; and
etching the first material layer by a process which forms grooves in the photoresist.
A third illustrative embodiment includes a method of integrated circuit fabrication which includes forming a transistor upon a substrate;
forming a first dielectric overlying the substrate and the transistor;
forming an opening within the first dielectric; the opening being defined by a wall with grooves;
forming at least one first conductive material within the opening, the first conductive material having a respective wall with grooves;
forming a second dielectric covering a portion of the wall of the first conductive material; and
forming a second conductor covering the second dielectric.
A fourth illustrative embodiment includes an integrated circuit which includes:
a first conductor having a wall with grooves;
a dielectric contacting the conductor;
a second dielectric contacting the dielectric;
the first and second conductors and the dielectric together comprising a capacitor.
A fifth illustative embodiment includes an integrated circuit which includes:
a transistor;
a first dielectric covering the transistor;
a conductive plug partially embedded in said dielectric; the conductive plug having a top and a wall, the wall having grooves;
a second dielectric covering the plug top and a portion of the grooved wall; and
a patterned conductive layer covering the second dielectric.